MC68HC908MR8 Datasheet, PDF (242/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface B (TIMB)
12.10.4 TIMB Channel Status and Control Registers
Each of the TIMB channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIMB overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register Name and Ad-
dress:
TBSC0 — $0056
Bit 7
6
5
4
Read: CH0F
CH0IE MS0B MS0A
Write: 0
Reset: 0
0
0
0
3
2
ELS0B ELS0A
0
0
1
TOV0
0
Bit 0
CH0MA
X
0
Register Name and Ad-
dress:
TBSC1 — $0059
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH1F
CH1IE
Write: 0
0
R
MS1A
ELS1B ELS1A
TOV1
CH1MA
X
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 12-7. TIMB Channel Status and Control Registers
(TBSC0–TBSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMB
counter registers matches the value in the TIMB channel x registers.
Technical Data
242
Timer Interface B (TIMB)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor