MC68HC908MR8 Datasheet, PDF (159/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control (PWMMC)
Output Control
9.6.4 Output Port Control Register
Conditions may arise in which the PWM pins need to be individually
controlled. This is made possible by the PWM output control register
(PWMOUT) shown in Figure 9-18.
Ad-
dress:
$0025
BIt 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
OUT-
CTL
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
Reset: 0
0
0
0
0
0
0
0
= Unimplement-
ed
Figure 9-18. PWM Output Control Register (PWMOUT)
If the OUTCTL bit is set, the PWM pins can be controlled by the OUTx
bits. These bits behave according to Table 9-4.
Table 9-4. OUTx Bits
OUTx Bit
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
Complementary Mode
1 — PWM1 is active.
0 — PWM1 is inactive.
1 — PWM2 is complement of PWM1.
0 — PWM2 is inactive.
1 — PWM3 is active.
0 — PWM3 is inactive.
1 — PWM4 is complement of PWM3.
0 — PWM4 is inactive.
1 — PWM5 is active.
0 — PWM5 is inactive.
1 — PWM6 is complement of PWM5.
0 — PWM6 is inactive.
Independent Mode
1 — PWM1 is active
0 — PWM1 is inactive
1 — PWM2 is active
0 — PWM2 is inactive
1 — PWM3 is active
0 — PWM3 is inactive
1 — PWM4 is active
0 — PWM4 is inactive
1 — PWM5 is active
0 — PWM5 is inactive
1 — PWM6 is active
0 — PWM6 is inactive
When OUTCTL is set, the polarity options TOPPOL and BOTPOL will
still affect the outputs. In addition, if complementary operation is in use,
the PWM pairs will not be allowed to be active simultaneously, and
dead-time will still not be violated. When OUTCTL is set and
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC)
Technical Data
159