MC68HC908MR8 Datasheet, PDF (181/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control (PWMMC)
Control Logic Block
FINT4 — Fault 4 Interrupt Enable Bit
This read/write bit allows the CPU interrupt caused by faults on fault
pin 4 to be enabled. The fault protection circuitry is independent of this
bit and will always be active. If a fault is detected, the PWM pins will
still be disabled according to the disable mapping register.
1 = Fault pin 4 will cause CPU interrupts.
0 = Fault pin 4 will not cause CPU interrupts.
9.12.9 Fault Status Register
This read-only register indicates the current fault status.
Ad-
dress:
$0023
Bit 7
6
5
4
3
2
1
Bit 0
Read: FPIN4
FFLAG
4
0
0
0
0
FPIN1
FFLAG
1
Write:
Reset: U
0
U
0
U
0
U
0
= Unimplement-
ed
U = Unaffected
Figure 9-40. Fault Status Register (FSR)
FFLAG1 — Fault Event Flag 1
The FFLAG1 event bit is set within two CPU cycles after a rising edge
on fault pin 1. To clear the FFLAG1 bit, the user must write a 1 to the
FTACK1 bit in the fault acknowledge register.
1 = A fault has occurred on fault pin 1
0 = No new fault on fault pin 1
FPIN1 — State of Fault Pin 1
This read-only bit allows the user to read the current state of fault
pin 1.
1 = Fault pin 1 is at logic 1
0 = Fault pin 1 is at logic 0
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC)
Technical Data
181