MC68HC908MR8 Datasheet, PDF (165/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control (PWMMC)
Fault Protection
non-fault condition to facilitate the use of PORTC as an output pin and
not interfere with the PWM generator. To regain the fault capability for
the respective fault input pin, clear the PORTC data direction register bit
for that pin.
Additionally, when the device is reset, by default, PORTC is configured
as an input. If either bit(s) of PORTC is intended to be used as an output,
the logic state of the driven device’s input is indeterminate. The state of
the driven device, if at a logic one will drive the respective bit of PORTC
input high, thus causing a fault to be input to the respective PORTC input
and to the PWM module.
After setting the PORTC data direction register, clear the respective fault
bits by writing a 1 to bit(s) 0 and or bit 6 in the FTACK Fault Acknowledge
Register (FTACK) and Fault Status Registers (FSR), based on which
PORTC bits that are used as output(s).
9.7.1.1 Fault Pin Filter
The two fault pins incorporate a filter to assist in determining a genuine
fault condition. After a fault pin has been logic low for one CPU cycle, a
rising edge (logic high) will be synchronously sampled once per CPU
cycle for two cycles. If both samples are detected logic high, the
corresponding FPIN bit and FFLAG bit will be set. The FPIN bit will
remain set until the corresponding fault pin is logic low and
synchronously sampled once in the following CPU cycle.
9.7.1.2 Automatic Mode
In automatic mode, the PWM(s) are disabled immediately once a filtered
fault condition is detected (logic high). The PWM(s) remain disabled until
the filtered fault condition is cleared (logic low) and a new PWM cycle
begins as shown in Figure 9-24. Clearing the corresponding FFLAGx
event bit will not enable the PWMs in automatic mode.
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC)
Technical Data
165