MC68HC908MR8 Datasheet, PDF (246/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface B (TIMB)
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the
TIMB channel x registers (TBCHxH) inhibits input captures until the low
byte (TBCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of
the TIMB channel x registers (TBCHxH) inhibits output compares until
the low byte (TBCHxL) is written.
Register Name and Address:
TBCH0H — $0057
Bit 7
6
5
4
3
2
Read:
Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Reset:
Indeterminate after reset
1
Bit 9
Bit 0
Bit 8
Register Name and Address:
TBCH0L — $0058
Bit 7 6
5
4
3
2
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reset:
Indeterminate after reset
1
Bit 1
Bit 0
Bit 0
Register Name and Address:
TBCH1H — $005A
Bit 7
6
5
4
3
2
Read:
Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Reset:
Indeterminate after reset
1
Bit 9
Bit 0
Bit 8
Register Name and Address:
TBCH1L — $005B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
Indeterminate after reset
Figure 12-9. TIMB Channel Registers (TBCH0H/L–TBCH1H/L)
Technical Data
246
Timer Interface B (TIMB)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor