MC68HC908MR8 Datasheet, PDF (85/372 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
Instruction Set Summary
Table 6-1. Instruction Set Summary (Sheet 7 of 8)
Source
Form
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
SEC
SEI
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
STHX opr
STOP
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Operation
Subtract with Carry
Set Carry Bit
Set Interrupt Mask
Store A in M
Store H:X in M
Enable IRQ Pin; Stop Oscillator
Store X in M
Subtract
SWI
Software Interrupt
TAP
Transfer A to CCR
TAX
Transfer A to X
TPA
Transfer CCR to A
Description
A ← (A) – (M) – (C)
C←1
I←1
M ← (A)
(M:M + 1) ← (H:X)
I ← 0; Stop Oscillator
M ← (X)
A ← (A) – (M)
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ¨ (SP) – 1; I ¨ 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
CCR ← (A)
X ← (A)
A ← (CCR)
Effect on CCR
VH I NZC
IMM
DIR
EXT
↕
– –↕
↕
↕
IX2
IX1
IX
SP1
SP2
– – – – – 1 INH
– – 1 – – – INH
DIR
EXT
IX2
0 – – ↕ ↕ – IX1
IX
SP1
SP2
0 – – ↕ ↕ – DIR
– – 0 – – – INH
DIR
EXT
IX2
0 – – ↕ ↕ – IX1
IX
SP1
SP2
IMM
DIR
EXT
↕
– –↕
↕
↕
IX2
IX1
IX
SP1
SP2
– – 1 – – – INH
↕ ↕ ↕ ↕ ↕ ↕ INH
– – – – – – INH
– – – – – – INH
A2 ii
2
B2 dd 3
C2 hh ll 4
D2 ee ff 4
E2 ff
3
F2
2
9EE2 ff
4
9ED2 ee ff 5
99
1
9B
2
B7 dd 3
C7 hh ll 4
D7 ee ff 4
E7 ff
3
F7
2
9EE7 ff
4
9ED7 ee ff 5
35 dd 4
8E
1
BF dd 3
CF hh ll 4
DF ee ff 4
EF ff
3
FF
2
9EEF ff
4
9EDF ee ff 5
A0 ii
2
B0 dd 3
C0 hh ll 4
D0 ee ff 4
E0 ff
3
F0
2
9EE0 ff
4
9ED0 ee ff 5
83
9
84
2
97
1
85
1
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Central Processor Unit (CPU)
Technical Data
85