MC68HC908MR8 Datasheet, PDF (225/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface B (TIMB)
Features
INTERNAL
BUS CLOCK
PRESCALER
PRESCALER SELECT
TSTOP
TRST
16-BIT COUNTER
16-BIT COMPARATOR
TMODH:TMODL
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
16-BIT LATCH
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
16-BIT LATCH
PS2
PS1
PS0
ELS0B ELS0A
CH0F
MS0A
ELS1B ELS1A
MS0B
MS1A
CH1F
TOF
TOIE
TOV0
CH0MAX
CH0IE
TOV1
CH1MAX
CH1IE
Figure 12-1. TIMB Block Diagram
INTERRUPT
LOGIC
PTB5
LOGIC
INTERRUPT
LOGIC
PTB5/TCH0B
PTB6
LOGIC
INTERRUPT
LOGIC
PTB6/TCH1B
Addr.
Register Name
Bit 7
6
5
4
3
2
Read
:
TOF
0
0
TIMB Status/Control Regis-
TOIE TSTOP
PS2
$0051
ter Write
(TBSC) :
0
TRST R
See page 238.
Re-
set:
0
0
1
0
0
0
Read
:
$0052
TIMB Counter Register High
(TBCNTH)
See page 240.
Write
:
Re-
set:
Bit 15
R
0
Bit 14
R
0
Bit 13
R
0
Bit 12
R
0
Bit 11
R
0
Bit 10
R
0
R = Reserved
Figure 12-2. TIMB I/O Register Summary
1
PS1
0
Bit 9
R
0
Bit 0
PS0
0
Bit 8
R
0
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Timer Interface B (TIMB)
Technical Data
225