MC68HC908MR8 Datasheet, PDF (47/372 Pages) Motorola, Inc – Microcontrollers

Memory Map
I/O Section
Addr.
Register Name
Bit 7
6
IRQ Status/Control Reg- Read: 0
0
$003F
ister
(ISCR)
Write:
R
R
See page 303. Reset: 0
0
ADC Status and Control ^Read: _COCO
$0040
Register (ADSCR) Write:
See page 319. _{Reset: 0}
AIEN
0
ADC Data Register High ^{Read: 0}
0
$0041
(ADRH) Write: R
R
See page 322. _Reset:
ADC Data Register Low ^{Read: AD7 AD6}
$0042
(ADRL) Write: R
R
See page 323. _Reset:
$0043
ADC Clock Register ^Read: _ADIV2
(ADCLK) Write:
See page 324. _{Reset: 0}
ADIV1
0
$0044
↓
$0050
5
0
R
0
ADCO
0
0
R
AD5
R
ADIV0
0
4
3
2
1
Bit 0
0
0
IRQF
IMASK1 MODE1
R
ACK1
0
0
0
0
0
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
1
1
1
1
1
0
0
0
AD9 AD8
R
R
R
R
R
Unaffected by reset
AD4
AD3
AD2 AD1 AD0
R
R
R
R
R
Unaffected by reset
0
ADICLK MODE1 MODE0 0
R
0
0
1
0
0
Unimplemented
Unimplemented
$0051
TIMB Status/Control ^Read:
Register (TBSC) Write:
See page 238. _Reset:
TOF
0
0
TOIE TSTOP
0
1
$0052
TIMB Counter Register Read: Bit 15
High
(TBCNTH)
Write:
R
See page 240. Reset: 0
Bit 14
R
0
Bit 13
R
0
$0053
TIMB Counter Register Read;
Low
(TBCNTL)
Write:
See page 240. Reset:
Bit 7
R
0
Bit 6
R
0
Bit 5
R
0
$0054
TIMB Counter Modulo Read:
Register High (TB-
MODH)
Write:
Bit 15
See page 241. Reset: 1
Bit 14
1
Bit 13
1
U = Unaffected X = Indetermi-
nate
R ^{= Reserved}
0
TRST
0
Bit 12
R
0
Bit 4
R
0
0
R
0
Bit 11
R
0
Bit 3
R
0
Bit 12 Bit 11
1
Bold
1
= Buff-
ered
PS2 PS1 PS0
0
Bit 10
R
0
Bit 2
R
0
0
Bit 9
R
0
Bit 1
R
0
0
Bit 8
R
0
Bit 0
R
0
Bit 10 Bit 9 Bit 8
1
1
1
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 10)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Memory Map
Technical Data
47