MC68HC908MR8 Datasheet, PDF (182/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control
FFLAG4 — Fault Event Flag 4
The FFLAG4 event bit is set within two CPU cycles after a rising edge
on fault pin 4. To clear the FFLAG4 bit, the user must write a 1 to the
FTACK4 bit in the fault acknowledge register.
1 = A fault has occurred on fault pin 4
0 = No new fault on fault pin 4
FPIN4 — State of Fault Pin 4 Bit
This read-only bit allows the user to read the current state of fault
pin 4.
1 = Fault pin 4 is at logic 1.
0 = Fault pin 4 is at logic 0.
9.12.10 Fault Acknowledge Register
The fault acknowledge register (FTACK) is used to acknowledge and
clear the FFLAGs. In addition, it is used to monitor the current sensing
bits to test proper operation.
Ad-
dress:
$0024
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
0
0
0
Write:
FTACK
4
Reset: 0
0
0
0
0
0
0
= Unimplement-
ed
Figure 9-41. Fault Acknowledge Register (FTACK)
Bit 0
0
FTACK
1
0
Technical Data
182
MC68HC908MR8 — Rev 4.1
Pulse-Width Modulator for Motor Control (PWMMC) Freescale Semiconductor