MC68HC908MR8 Datasheet, PDF (324/372 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
In 8-bit mode, this 8-bit result register holds the eight MSBs of the 10-bit
result. This register is updated each time an ADC conversion completes.
In 8-bit mode, this register contains no interlocking with ADRH.
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Bit 7
6
5
4
3
2
1
Bit 0
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write: R
R
R
R
R
R
R
R
Reset:
Unaffected by Reset
R = Reserved
Figure 18-8. ADC Data Register Low (ADRL)
8-Bit Mode
18.9.4 ADC Clock Register
This register selects the clock frequency for the ADC, selecting between
modes of operation.
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Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 0
Write:
R
Reset: 0
0
0
0
0
1
0
0
R = Reserved
Figure 18-9. ADC Clock Register (ADCLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 18-2
shows the available clock configurations. The ADC clock should be
set to between 500 kHz and 1 MHz.
Technical Data
324
Analog-to-Digital Converter (ADC)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor