MC68HC908MR8 Datasheet, PDF (323/372 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
I/O Registers
18.9.3 ADC Data Register Low
In left justified mode, this 8-bit result register holds the two LSBs of the
10-bit result. All other bits read as 0. This register is updated each time
a single channel ADC conversion completes. Reading ADRH latches the
contents of ADRL until ADRL is read. Until ADRL is read all subsequent
ADC results will be lost.
Ad-
dress:
$0042
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD1 AD0
0
0
0
0
0
0
Write: R
R
R
R
R
R
R
R
Reset:
Unaffected by Reset
R = Reserved
Figure 18-6. ADC Data Register Low (ADRL)
Left Justified Mode
In right justified mode, this 8-bit result register holds the eight LSBs of
the 10-bit result. This register is updated each time an ADC conversion
completes. Reading ADRH latches the contents of ADRL until ADRL is
read. Until ADRL is read all subsequent ADC results will be lost.
Ad-
dress:
$0042
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write: R
R
R
R
R
R
R
R
Reset:
Unaffected by Reset
R = Reserved
Figure 18-7. ADC Data Register Low (ADRL)
Right Justified Mode
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
Technical Data
323