MC68HC908MR8 Datasheet, PDF (244/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface B (TIMB)
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port B, and pin PTBx/TCHxB is available as a general-purpose I/O
pin. However, channel x is at a state determined by these bits and
becomes transparent to the respective pin when PWM, input capture,
or output compare mode is enabled. Table 12-2 shows how ELSxA
and ELSxA work. Reset clears the ELSxB and ELSxA bits.
Table 12-2. Mode, Edge, and Level Selection
MSxB:MSxA
X0
X1
00
00
00
01
01
01
1X
1X
1X
ELSxB:ELSxA
00
00
01
10
11
01
10
11
01
10
11
Mode
Output
preset
Input
capture
Output
compare
or PWM
Buffered
output
compare
or
buffered
PWM
Configuration
Pin under port control;
Initialize timer
Output level high
Pin under port control;
Initialize timer
Output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
NOTE: Before enabling a TIMB channel register for input capture operation,
make sure that the PTBx/TBCHx pin is stable for at least two bus clocks.
Technical Data
244
Timer Interface B (TIMB)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor