MC68HC908MR8 Datasheet, PDF (126/372 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
Addr.
Register Name
Bit 7 6
5
4
3
2
1 Bit 0
$005E
Read
:
PLL Programming Register
(PPG)
See page 131.
Write
:
MUL7
Re-
set:
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6
1
VRS5
1
VRS4
0
R = Reserved
Notes:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 8-4. CGM I/O Register Summary
8.6.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, and the base clock selector bit.
Ad- $005C
dress:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLLIE
PLLON BCS
Write:
R
R
R
R
R
Reset: 0
0
1
0
1
1
1
1
R = Reserved
Figure 8-5. PLL Control Register (PCTL)
Technical Data
126
Clock Generator Module (CGM)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor