MC68HC908MR8 Datasheet, PDF (166/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control
FILTERED FAULT PIN
PWM(s) ENABLED
PWM(S) DISABLED (INACTIVE)
PWM(S) ENABLED
Figure 9-24. PWM Disabling in Automatic Mode
The filtered fault pin’s logic state is reflected in the respective FPINx bit.
Any write to this bit is overwritten by the pin state. The FFLAGx event bit
is set with each rising edge of the respective fault pin after filtering has
been applied. To clear the FFLAGx bit, the user must write a 1 to the
corresponding FTACKx bit.
If the FINTx bit is set, a fault condition resulting in setting the
corresponding FFLAG bit will also latch a CPU interrupt request. The
interrupt request latch is not cleared until one of these actions occurs:
• The FFLAGx bit is cleared by writing a 1 to the corresponding
FTACKx bit.
• The FINTx bit is cleared. (This will not clear the FFLAGx bit.)
• Reset — A reset automatically clears all four interrupt latches.
If prior to a vector fetch the interrupt request latch is cleared by one of
the above actions, a CPU interrupt will no longer be requested. A vector
fetch does not alter the state of the PWMs, the FFLAGx event flag, or
FINTx.
NOTE: If the FFLAGx or FINTx bits are not cleared during the interrupt service
routine, the interrupt request latch will not be cleared.
Technical Data
166
MC68HC908MR8 — Rev 4.1
Pulse-Width Modulator for Motor Control (PWMMC) Freescale Semiconductor