MC68HC908MR8 Datasheet, PDF (302/372 Pages) Motorola, Inc – Microcontrollers

External Interrupt (IRQ)
16.6 IRQ Module During Wait Mode
The IRQ module remains active in wait mode. Clearing the IMASK1 bit
in the IRQ status and control register (ISCR) enables IRQ central
processor unit (CPU) interrupt requests to bring the microcontroller unit
(MCU) out of wait mode.
16.7 IRQ Module During Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK1 bit
in the IRQ status and control register (ISCR) enables IRQ CPU interrupt
requests to bring the MCU out of stop mode.
16.8 IRQ Module During Break Mode
The system integration (SIM) module controls whether the IRQ interrupt
latch can be cleared during the break state. The BCFE bit in the SIM
break flag control register (SBFCR) enables software to clear the latches
during the break state. See 7.7.5 SIM Break Flag Control Register.
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK1 bit in the
IRQ status and control register during the break state has no effect on
the IRQ latches. See 16.9 IRQ Status and Control Register.
Technical Data
302
External Interrupt (IRQ)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor