MC68HC908MR8 Datasheet, PDF (164/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control
BIT 7
DISABLE
PWM PIN 1
BIT 6
DISABLE
BIT 5
PWM PIN 2
BIT 4
BANK X
DISABLE
BIT 3
BANK Y
DISABLE
DISABLE
PWM PIN 3
DISABLE
PWM PIN 4
BIT 2
DISABLE
BIT 1
PWM PIN 5
BIT 0
DISABLE
PWM PIN 6
Figure 9-23. PWM Disabling Decode Scheme
9.7.1 Fault Condition Input Pins
A logic high level on a fault pin disables the respective PWM(s)
determined by the bank and the disable mapping register. Each fault pin
incorporates a filter to assist in rejecting spurious faults. All of the
external fault pins are software-configurable to re-enable the PWMs
either with the fault pin (automatic mode) or with software (manual
mode). Each fault pin has an associated FMODE bit to control the PWM
re-enabling method. Automatic mode is selected by setting the FMODEx
bit in the fault control register. Manual mode is selected when FMODEx
is clear.
NOTE:
PORTC, when used as an input port, mirrors the state of the fault input
pins, as PORTC has the capability of being used as an output port.
When either pin of PORTC is set as an output, by setting its respective
PORTC data direction register bit, the respective fault pin logic is
disconnected from that pin and the fault input will be defaulted to normal
Technical Data
164
MC68HC908MR8 — Rev 4.1
Pulse-Width Modulator for Motor Control (PWMMC) Freescale Semiconductor