MC68HC908MR8 Datasheet, PDF (48/372 Pages) Motorola, Inc – Microcontrollers

Memory Map
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
TIMB Counter Modulo ^Read:
$0055 Register Low (TBMODL) Write:
See page 241. _Reset:
Bit 7
1
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1 Bit 0
1
1
$0056
TIMB Channel 0 Sta- Read: CH0F
tus/Control Register
(TBSC0)
Write:
0
See page 242. Reset: 0
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
TOV0
CH0MA
X
0
0
$0057
TIMB Channel 0 Regis- ^Read: _{Bit 15}
ter High (TBCH0H) Write:
See page 246. _Reset:
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10
Indeterminate after reset
Bit 9
Bit 8
$0058
TIMB Channel 0 Regis- ^Read:
ter Low (TBCH0L) Write:
See page 246. _Reset:
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Indeterminate after reset
Bit 1
Bit 0
TIMB Channel 1 Sta- Read: CH1F
0
$0059
tus/Control Register
(TBSC1)
Write:
0
CH1IE
R
See page 242. Reset: 0
0
0
MS1A
0
ELS1B
0
ELS1A
0
TOV1
CH1MA
X
0
0
$005A
TIMB Channel 1 Regis- ^Read: _{Bit 15}
ter High (TBCH1H) Write:
See page 246. _Reset:
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10
Indeterminate after reset
Bit 9
Bit 8
$005B
TIMB Channel 1 Regis- ^Read:
ter Low (TBCH1L) Write:
See page 246. _Reset:
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Indeterminate after reset
Bit 1
Bit 0
PLL Control Register ^Read: _PLLIE ^PLLF _{PLLON BCS}
1
$005C
(PCTL) Write:
R
R
See page 126. _{Reset: 0}
0
1
0
1
1
1
1
R
R
R
1
1
1
PLL Bandwidth Control ^Read: _AUTO ^LOCK _ACQ
XLD
0
$005D
Register (PBWC) Write:
R
R
See page 129. _{Reset: 0}
0
0
0
0
0
0
0
R
R
R
0
0
0
$005E
PLL Programming Reg- Read:
ister
(PPG)
Write:
See page 131. Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6 VRS5 VRS4
1
1
0
U = Unaffected X = Indetermi-
nate
R ^{= Reserved}
Bold
= Buff-
ered
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 10)
Technical Data
48
Memory Map
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor