MC68HC908MR8 Datasheet, PDF (219/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface A (TIMA)
I/O Registers
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMA
counter registers matches the value in the TIMA channel x registers.
When CHxIE = 1, clear CHxF by reading TIMA channel x status and
control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x. Reset
clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMA channel 0. Setting MS0B disables the
channel 1 status and control register and reverts TCH1A to
general-purpose I/O. Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. See
Table 11-2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin once PWM, input capture, or output compare
operation is enabled. Reset clears the MSxA bit. See Table 11-2.
1 = Initial output level low
0 = Initial output level high
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Timer Interface A (TIMA)
Technical Data
219