MC68HC908MR8 Datasheet, PDF (237/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface B (TIMB)
TIMB Channel I/O Pins (PTB5/TCH0B–PTB6/TCH1B)
12.9 TIMB Channel I/O Pins (PTB5/TCH0B–PTB6/TCH1B)
Port B shares two of its pins with the TIMB. The two TIMB channel I/O
pins are PTB5/TCH0B and PTB6/TCH1B.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTB5/TCH0B and PTB6/TCH1B
can be configured as buffered output compare or buffered PWM pins.
12.10 I/O Registers
These I/O registers control and monitor TIMB operation:
• TIMB status and control register (TBSC)
• TIMB control registers (TBCNTH–TBCNTL)
• TIMB counter modulo registers (TBMODH–TBMODL)
• TIMB channel status and control registers (TBSC0 and TBSC1)
• TIMB channel registers (TBCH0H–TBCH0L and
TBCH1H–TBCH1L)
12.10.1 TIMB Status and Control Register
The TIMB status and control register:
• Enables TIMB overflow interrupts
• Flags TIMB overflows
• Stops the TIMB counter
• Resets the TIMB counter
• Prescales the TIMB counter clock
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Timer Interface B (TIMB)
Technical Data
237