MC68HC908MR8 Datasheet, PDF (137/372 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
This equation does not always yield a commonly available capacitor
size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL can become unstable. Also, always choose a capacitor with a tight
tolerance (±20 percent or better) and low dissipation.
8.11.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the
equations here. These equations yield nominal values under these
conditions:
• Correct selection of filter capacitor, C_F; see 8.11.3 Choosing a
Filter Capacitor
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K_ACQ is the K factor when the PLL is configured in acquisition mode, and
K_TRK is the K factor when the PLL is configured in tracking mode. See
8.4.2.2 Acquisition and Tracking Modes.
tACQ
=



V--f--R-D---D-D----V-A---_{}


K-----A---8-C-----Q---^
tAL
=
 ^{-V-f--R-D---D-D----V-A---}


K-----T--4--R----K---^
tLock = tACQ + tAL
NOTE:
Inverse proportionality between the lock time and the reference
frequency
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency, see 8.4.2.3
Manual and Automatic PLL Bandwidth Modes. A certain number of
clock cycles, n_ACQ, is required to ascertain that the PLL is within the
tracking mode entry tolerance, ∆_TRK, before exiting acquisition mode. A
MC68HC908MR8 — Rev 4.1
Technical Data
Freescale Semiconductor
Clock Generator Module (CGM)
137