MC68HC908MR8 Datasheet, PDF (177/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control (PWMMC)
Control Logic Block
NOTE: A PWM CPU interrupt request can still be generated when LDOK is 0.
9.12.5 PWM Control Register 2
PWM control register 2 controls the PWM load frequency, the PWM
correction method, and the PWM counter prescaler. For ease of
software and to avoid erroneous PWM periods, some of these register
bits are buffered. The PWM generator will not use the prescaler value
until the LDOK bit has been set, and a new PWM cycle is starting. The
correction bits are used at the beginning of each PWM cycle (if the
ISENSx bits are configured for software correction). The load frequency
bits are not used until the current load cycle is complete.
NOTE: The user should initialize this register before enabling the PWM.
Ad-
dress:
$0021
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
LDFQ1 LDFQ0
SEL12 SEL34 SEL56 PRSC1 PRSC0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplement-
ed
Bold ^{= Buffered}
Figure 9-36. PWM Control Register 2 (PCTL2)
LDFQ1 and LDFQ0 — PWM Load Frequency Bits
These buffered read/write bits select the PWM CPU load frequency
according to Table 9-5.
NOTE:
When reading these bits, the value read is the buffer value (not
necessarily the value the PWM generator is currently using).
Table 9-5. PWM Reload Frequency
Reload Frequency Bits
LDFQ1:LDFQ0
00
01
10
11
PWM Reload Frequency
Every PWM cycle
Every 2 PWM cycles
Every 4 PWM cycles
Every 8 PWM cycles
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC)
Technical Data
177