MC68HC908MR8 Datasheet, PDF (222/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface A (TIMA)
11.10.5 TIMA Channel Registers
These read/write registers contain the captured TIMA counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the
TIMA channel x registers (TACHxH) inhibits input captures until the low
byte (TACHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of
the TIMA channel x registers (TACHxH) inhibits output compares until
the low byte (TACHxL) is written.
Register Name and Address:
Bit 7
6
5
TACH0H — $0014
4
3
2
1
Bit 0
Read:
Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after reset
Register Name and Address:
TACH0L — $0015
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
Indeterminate after reset
Register Name and Address:
TACH1H — $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after reset
Register Name and Address:
TACH1L — $0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
Indeterminate after reset
Figure 11-9. TIMA Channel Registers (TACH0H/L–TACH1H/L)
Technical Data
222
Timer Interface A (TIMA)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor