MC68HC908MR8 Datasheet, PDF (235/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface B (TIMB)
Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H–TBCH0L)
initially control the buffered PWM output. TIMB status control register 0
(TBSC0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMB overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0 percent duty
cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100 percent duty cycle output. See 12.10.4 TIMB
Channel Status and Control Registers.
12.5 Interrupts
These TIMB sources can generate interrupt requests:
• TIMB overflow flag (TOF) — The TOF bit is set when the TIMB
counter reaches the modulo value programmed in the TIMB
counter modulo registers. The TIMB overflow interrupt enable bit,
TOIE, enables TIMB overflow CPU interrupt requests. TOF and
TOIE are in the TIMB status and control register.
• TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMB CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
12.6 Wait Mode
The WAIT instruction puts the MCU in low-power standby mode.
The TIMB remains active after the execution of a WAIT instruction. In
wait mode, the TIMB registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMB can bring the MCU out of
wait mode.
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Timer Interface B (TIMB)
Technical Data
235