MC68HC908MR8 Datasheet, PDF (212/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface A (TIMA)
If TIMA functions are not required during wait mode, reduce power
consumption by stopping the TIMA before executing the WAIT
instruction.
11.7 Stop Mode
TIMA is inactive after execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIMA
counter. TIMA operation resumes when the MCU exits stop mode after
an external interrupt.
11.8 TIMA During Break Interrupts
A break interrupt stops the TIMA counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 7.7.5 SIM Break Flag Control
Register.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
11.9 I/O Signals
Port B shares three of its pins with the TIMA. PTB2/TCLKA is an external
clock input to the TIMA prescaler. The two TIMA channel I/O pins are
PTB3/TCH0A and PTB4/TCH1A.
Technical Data
212
Timer Interface A (TIMA)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor