MC68HC908MR8 Datasheet, PDF (56/372 Pages) Motorola, Inc – Microcontrollers

FLASH Memory
4.2.1 Functional Description
The FLASH memory physically consists of an array of 7680 bytes with
an additional 46 bytes of user vectors and one byte of block protection.
An erased bit reads as a logic 1 and a programmed bit reads as a logic 0.
Program and erase operations are facilitated through control bits in a
memory mapped register. Details for these operations appear later in
this section.
Memory in the FLASH array is organized into two rows per page base.
For the 8-K word by 8-bit embedded FLASH memory, the page size is
64 bytes per page. The minimum erase page size is 64 bytes. Program
and erase operations are performed through control bits in the FLASH
control register (FLCR).
The address ranges for the user memory, control register, and vectors
are:
• $E000–$FDFF, user memory
• $FF7E, block protect register (FLBPR)
• $FE08, FLASH control register (FLCR)
• $FFD2–$FFFF, locations reserved for user-defined interrupt and
reset vectors
NOTE:
Programming tools are available from Freescale. Contact a local
Freescale representative for more information.
A security feature¹ prevents viewing of the FLASH contents.
Technical Data
56
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
FLASH Memory
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor