MC68HC908MR8 Datasheet, PDF (180/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control
9.12.8 Fault Control Register
This register controls the fault protection circuitry.
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Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
FINT4
FMODE
4
FINT1
FMODE
1
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-39. Fault Control Register (FCR)
FMODE1 — Fault Mode Selection for Fault Pin 1 Bit (Automatic versus
Manual Mode)
This read/write bit allows the user to select between automatic and
manual mode faults. For further description of each mode, see
9.7 Fault Protection.
1 = Automatic mode
0 = Manual mode
FINT1 — Fault 1 Interrupt Enable Bit
This read/write bit allows the CPU interrupt caused by faults on fault
pin 1 to be enabled. The fault protection circuitry is independent of this
bit and will always be active. If a fault is detected, the PWM pins will
still be disabled according to the disable mapping register.
1 = Fault pin 1 will cause CPU interrupts.
0 = Fault pin 1 will not cause CPU interrupts.
FMODE4 — Fault Mode Selection for Fault Pin 4 Bit (Automatic versus
Manual Mode)
This read/write bit allows the user to select between automatic and
manual mode faults. For further description of each mode, see
9.7 Fault Protection.
1 = Automatic mode
0 = Manual mode
Technical Data
180
MC68HC908MR8 — Rev 4.1
Pulse-Width Modulator for Motor Control (PWMMC) Freescale Semiconductor