MC68HC908MR8 Datasheet, PDF (42/372 Pages) Motorola, Inc – Microcontrollers

Memory Map
Addr.
Register Name
Bit 7
Read:
Data Direction Register
U
$0005
B
(DDRB)
Write:
See page 284. Reset: _U
6
5
4
DDRB6 DDRB5 DDRB4
0
0
0
3
DDRB3
0
2
1
Bit 0
DDRB2 DDRB1 DDRB0
0
0
0
Read:
Data Direction Register
$0006
C
(DDRC)
Write:
DDRC1 DDRC0
See page 288. Reset: _U
U
U
U
U
U
0
0
$0007
↓
$000D
Unimplemented
Unimplemented
$000E
TIMA Status/Control ^Read:
Register (TASC) Write:
See page 214. _Reset:
TOF
0
0
TOIE TSTOP
0
1
$000F
TIMA Counter Register Read: Bit 15
High
(TACNTH)
Write:
R
See page 216. Reset: 0
Bit 14
R
0
Bit 13
R
0
$0010
TIMA Counter Register Read:
Low
(TACNTL)
Write:
See page 216. Reset:
Bit 7
R
0
Bit 6
R
0
Bit 5
R
0
TIMA Counter Modulo Read:
$0011
Register High
(TAMODH)
Write:
Bit 15
14
13
See page 217. Reset: 1
1
1
TIMA Counter Modulo ^Read: _{Bit 7}
6
5
$0012 Register Low (TAMODL) Write:
See page 217. _{Reset: 1}
1
1
$0013
TIMA Channel 0 Sta- Read: CH0F
tus/Control Register
(TASC0)
Write:
0
See page 218. Reset: 0
CH0IE
0
MS0B
0
U = Unaffected X = Indetermi-
nate
R ^{= Reserved}
0
TRST
0
Bit 12
R
0
Bit 4
R
0
0
R
0
Bit 11
R
0
Bit 3
R
0
12
11
1
1
4
3
1
1
MS0A ELS0B
0
Bold
0
= Buff-
ered
PS2 PS1 PS0
0
Bit 10
R
0
Bit 2
R
0
0
Bit 9
R
0
Bit 1
R
0
0
Bit 8
R
0
Bit 0
R
0
10
9
Bit 8
1
1
1
2
1
Bit 0
1
1
1
ELS0A
TOV0
CH0MA
X
0
0
0
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 10)
Technical Data
42
Memory Map
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor