MC68HC908MR8 Datasheet, PDF (175/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control (PWMMC)
Control Logic Block
9.12.4 PWM Control Register 1
PWM control register 1 controls PWM enabling/disabling, the loading of
new modulus, prescaler, and PWM values, and the PWM correction
method. In addition, this register contains the software disable bits to
force the PWM outputs to their inactive states (according to the disable
mapping register).
Ad-
dress:
$0020
Bit 7
6
5
4
3
2
1
Read:
DISX
Write:
DISY PWMINT PWMF
LDOK
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 9-35. PWM Control Register 1 (PCTL1)
Bit 0
PW-
MEN
0
DISX — Software Disable for Bank X Bit
This read/write bit allows the user to disable one or more PWM pins
in bank X. The pins that are disabled are determined by the disable
mapping write-once register.
1 = Disable PWM pins in bank X
0 = Re-enable PWM pins at beginning of next PWM cycle
DISY — Software Disable for Bank Y Bit
This read/write bit allows the user to disable one or more PWM pins
in bank Y. The pins that are disabled are determined by the disable
mapping write-once register.
1 = Disable PWM pins in Bank Y Bit
0 = Re-enable PWM pins at beginning of next PWM cycle
PWMINT — PWM Interrupt Enable Bit
This read/write bit allows the user to enable and disable PWM CPU
interrupts. If set, a CPU interrupt will be pending when the PWMF flag
is set.
1 = Enable PWM CPU interrupts
0 = Disable PWM CPU interrupts
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC)
Technical Data
175