MC68HC908MR8 Datasheet, PDF (150/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control
PWM RELOAD
V_DD
RESET
D
PWMF
LATCH
CK
PWMINT
READ PWMF AS 1,
WRITE PWMF AS 0
OR RESET
CPU INTERRUPT
REQUEST
Figure 9-6. PWM Interrupt Requests
To prevent a partial reload of PWM parameters from occurring while the
software is still calculating them, an interlock bit controlled from software
is provided. This bit informs the PWM module that all the PWM
parameters have been calculated, and it is okay to use them. A new
modulus, prescaler, and/or PWM value cannot be loaded into the PWM
module until the LDOK bit in PWM control register 1 is set. When the
LDOK bit is set, these new values are loaded into a second set of
registers and used by the PWM generator at the beginning of the next
PWM reload cycle as shown in Figure 9-7, Figure 9-8, Figure 9-9, and
Figure 9-10. After these values are loaded, the LDOK bit is cleared.
NOTE:
When the PWM module is enabled (via the PWMEN bit), a load will occur
if the LDOK bit is set. Even if it is not set, an interrupt will occur if the
PWMINT bit is set. To prevent this, the software should clear the
PWMINT bit before enabling the PWM module.
UP/DOWN
COUNTER
LDFQ1:LDFQ0 = 00 (RELOAD EVERY CYCLE)
Technical Data
150
LDOK = 1
MODULUS = 3
PWM VALUE= 1
PWMF SET
PWM
LDOK = 0
MODULUS = 3
PWM VALUE= 2
PWMF SET
LDOK = 1
MODULUS = 3
PWM VALUE= 2
PWMF SET
LDOK = 0
MODULUS = 3
PWM VALUE= 1
PWMF SET
Figure 9-7. Center-Aligned PWM Value Loading
MC68HC908MR8 — Rev 4.1
Pulse-Width Modulator for Motor Control (PWMMC) Freescale Semiconductor