MC68HC908MR8 Datasheet, PDF (213/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface A (TIMA)
I/O Registers
11.9.1 TIMA Clock Pin (PTB2/TCLKA)
PTB2/TCLKA is an external clock input that can be the clock source for
the TIMA counter instead of the prescaled internal bus clock. Select the
PTB2/TCLKA input by writing logic 1s to the three prescaler select bits,
PS[2:0] (see 11.10.1 TIMA Status and Control Register). The
minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is:
------------------1-------------------
bus frequency
+
tsu
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTB2/TCLKA is available as a general-purpose I/O pin or ADC channel
when not used as the TIMA clock input. When the PTB2/TCLKA pin is
the TIMA clock input, it is an input regardless of the state of the DDRB2
bit in data direction register B.
11.9.2 TIMA Channel I/O Pins (PTB3/TCH0A–PTB4/TCH1A)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTB3/TCH0A and PTB3/TCH1A
can be configured as buffered output compare or buffered PWM pins.
11.10 I/O Registers
These I/O registers control and monitor TIMA operation:
• TIMA status and control register (TASC)
• TIMA control registers (TACNTH–TACNTL)
• TIMA counter modulo registers (TAMODH–TAMODL)
• TIMA channel status and control registers (TASC0 and TASC1)
• TIMA channel registers (TACH0H–TACH0L and
TACH1H–TACH1L)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Timer Interface A (TIMA)
Technical Data
213