MC68HC908MR8 Datasheet, PDF (133/372 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
Wait Mode
frequency-sensitive, interrupts should be disabled to prevent PLL
interrupt service routines from impeding software performance or from
exceeding stack limitations.
NOTE:
Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
8.8 Wait Mode
The WAIT instruction puts the MCU in low power-consumption standby
mode.
The WAIT instruction does not affect the CGM. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
8.9 Stop Mode
The STOP instruction puts the MCU in low power-consumption standby
mode.
The STOP instruction disables the CGMC (oscillator and phase-lock
loop) and holds the CGM outputs low.
8.10 CGM During Break Mode
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 7.7.5 SIM Break Flag Control
Register.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
133