MC68HC908MR8 Datasheet, PDF (106/372 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
7.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clock is disabled.
An external interrupt request will cause an exit from stop mode. Stacking
for interrupts begins after the stop recovery delay time of 4096
CGMXCLK cycles has elapsed. Reset or break also cause an exit from
stop mode.
The SIM disables the clock generator module outputs in stop mode,
stopping the CPU and all peripherals.
NOTE:
It is important to note that when using the PWM generator Its outputs will
stop toggling when stop mode is entered. The PWM module must be
disabled before entering stop mode to prevent external inverter failure.
7.7.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from wait mode.
Ad- $FE00
dress:
BIt 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R
R
R
R
R
R
Write:
Note⁽¹⁾
Reset:
0
R = Reserved
1. Writing a logic 0 clears SBSW.
Figure 7-15. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This status bit is useful in applications requiring a return to wait mode
after exiting from a break interrupt. Clear SBSW by writing a logic 0 to
it. Reset clears SBSW.
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
Technical Data
106
System Integration Module (SIM)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor