MC68HC908MR8 Datasheet, PDF (332/372 Pages) Motorola, Inc – Microcontrollers

Break (BRK)
Read
:
$FE0
D
Break Address Regis-
ter Low (BRKL)
See page 334.
Write
:
Bit 7
6
5
Re-
set:
0
0
0
Read
:
0
Break Status and
BRKE BRKA
$FE0
Control Register Write
E
(BRKSCR) :
See page 333.
Re-
set:
0
0
0
Note: Writing a logic 0 clears
BW.
= Unimplemented
4
3
2
0
0
0
0
0
0
0
0
0
R ^{= Reserved}
Figure 20-2. I/O Register Summary
1
Bit 0
0
0
0
0
0
0
20.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
20.4.3 TIM During Break Interrupts
A break interrupt stops the timer counters.
20.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_TST is present on
the RST pin.
Technical Data
332
Break (BRK)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor