MC68HC908MR8 Datasheet, PDF (163/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control (PWMMC)
Fault Protection
pin 1 and PWM disable bit X constitute the disabling function of bank X.
Fault pin 4 and PWM disable bit Y constitute the disabling function of
bank Y. Figure 9-22 and Figure 9-23 show the disable mapping
write-once register and the decoding scheme of the bank which
selectively disables PWM(s). When all bits of the disable mapping
register are set, any disable condition will disable all PWMs.
A fault can also generate a CPU interrupt. Each fault pin has its own
interrupt vector.
Ad-
dress:
$0037
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset: 1
1
1
1
1
1
1
1
Figure 9-22. PWM Disable Mapping Write-Once Register (DISMAP)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC)
Technical Data
163