MC68HC908MR8 Datasheet, PDF (173/372 Pages) Motorola, Inc – Microcontrollers

Pulse-Width Modulator for Motor Control (PWMMC)
Control Logic Block
9.12.2 PWM Counter Modulo Registers
The PWM counter modulus registers (PDMODH and PDMODL) hold a
12-bit unsigned number that determines the maximum count for the
up/down or up-only counter. In center-aligned mode, the PWM period
will be twice the modulus (assuming no prescaler). In edge-aligned
mode, the PWM period will equal the modulus.
Ad-
dress:
$0028
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0
0
0
0
X
X
X
X
= Unimplemented X = Indeterminate
Figure 9-31. PWM Counter Modulo Register High (PDMODH)
Ad-
dress:
$0029
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset: X
X
X
X
X
X
X
X
= Unimplemented X = Indeterminate
Figure 9-32. PWM Counter Modulo Register Low (PDMODL)
To avoid erroneous PWM periods, this value is buffered and will not be
used by the PWM generator until the LDOK bit has been set and the next
PWM load cycle begins.
NOTE: When reading this register, the value read is the buffer (not necessarily
the value the PWM generator is currently using).
Because of the equals-comparator architecture of this PWM, the
modulus = 0 case is considered illegal. Therefore, the modulus register
is not reset, and a modulus value of 0 will result in waveforms
inconsistent with the other modulus waveforms. If a modulus of 0 is
loaded, the counter will continually count down from $FFF. This
operation will not be tested or guaranteed. (The user should consider it
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC)
Technical Data
173