MC68HC908MR8 Datasheet, PDF (135/372 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are:
• Acquisition time, t_ACQ, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance, ∆_TRK.
Acquisition time is based on an initial frequency error,
(f_DES– f_ORIG)/f_DES, of not more than ±100 percent. In automatic
bandwidth control mode (see 8.4.2.3 Manual and Automatic PLL
Bandwidth Modes), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
• Lock time, t_Lock, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance, ∆_Lock. Lock
time is based on an initial frequency error, (f_DES–f_ORIG)/f_DES, of
not more than ± 100 percent. In automatic bandwidth control
mode, lock time expires when the LOCK bit becomes set in the
PLL bandwidth control register (PBWC). See 8.4.2.3 Manual and
Automatic PLL Bandwidth Modes.
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
8.11.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL
is the reference frequency, f_RDV. This frequency is the input to the phase
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is also under user control via the choice of
crystal frequency, f_XCLK.
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
135