MC68HC908MR8 Datasheet, PDF (240/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface B (TIMB)
12.10.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes
of the value in the TIMB counter. Reading the high byte (TBCNTH)
latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL
is read. Reset clears the TIMB counter registers. Setting the TIMB reset
bit (TRST) also clears the TIMB counter registers.
NOTE:
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL
by reading TBCNTL before exiting the break interrupt. Otherwise,
TBCNTL retains the value latched during the break.
Register Name and Ad-
dress:
TBCNTH — $0052
Bit 7
6
5
4
3
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11
Write: R
R
R
R
R
Reset: 0
0
0
0
0
2
Bit 10
R
0
1
Bit 9
R
0
Bit 0
Bit 8
R
0
Register Name and Ad-
dress:
TBCNTL — $0053
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 12-5. TIMB Counter Registers (TBCNTH and TBCNTL)
Technical Data
240
Timer Interface B (TIMB)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor