MC68HC908MR8 Datasheet, PDF (298/372 Pages) Motorola, Inc – Microcontrollers

External Interrupt (IRQ)
16.4 Functional Description
A logic 0 applied to any of the external interrupt pins can latch a CPU
interrupt request. Figure 16-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
• Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (ISCR). Writing a logic 1 to the ACK1 bit clears the
IRQ latch.
• Reset — A reset automatically clears both interrupt latches.
ACK1
V_DD
D ^CLR Q
SYNCHRO-
IRQ
CK
NIZER
IRQ
LATCH
IMASK1
IRQ
INTERRUPT
REQUEST
MODE1
HIGH-
VOLTAGE
DETECT
Figure 16-1. IRQ Module Block Diagram
TO MODE
SELECT
LOGIC
Addr.
Register Name
Bit 7 6
5
4
3
2
1 Bit 0
IRQ Status/Control Register ^{Read: 0}
$003F
(ISCR) Write: R
0
R
0
R
0
R
IRQF
0 _{IMASK MODE}
ACK1 ¹
1
See page 303. _{Reset: 0}
0
0
0
0
0
0
0
R = Reserved
Figure 16-2. IRQ I/O Register Summary
Technical Data
298
External Interrupt (IRQ)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor