MC68HC908MR8 Datasheet, PDF (309/372 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
LVI Interrupts
Table 17-1. LVIOUT Bit Indication
At level:
V_LVRX < V_DD < V_LVRX + V_LVHX
V_DD
For number of CGMXCLK cycles:
Any
LVIOUT
Previous value
NOTE:
TRPSEL — LVI Trip Select Bit
This bit selects the LVI trip point. Reset clears this bit.
1 = 5 percent tolerance. The trip point and recovery point are
determined by V_LVR1 and V_LVH1 respectively.
0 = 10 percent tolerance. The trip point and recovery point are
determined by V_LVR2 and V_LVH2 respectively.
If LVIPWR and LVIRST are at logic 1, note that when changing the
tolerance, LVI reset will be generated if the supply voltage is below the
trip point.
17.6 LVI Interrupts
The LVI module does not generate interrupt requests.
17.7 Wait Mode
The WAIT instruction puts the microcontroller unit (MCU) in low
power-consumption standby mode.
With the LVIPWR bit in the configuration register programmed to logic 1,
the LVI module is active after a WAIT instruction.
With the LVIRST bit in the configuration register programmed to logic 1,
the LVI module can generate a reset and bring the MCU out of wait
mode.
17.8 Stop Mode
The STOP instruction puts the MCU in low power-consumption standby
mode.
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Low-Voltage Inhibit (LVI)
Technical Data
309