MC68HC908MR8 Datasheet, PDF (322/372 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
18.9.2 ADC Data Register High
In left justified mode, this 8-bit result register holds the eight MSBs of the
10-bit result. This register is updated each time an ADC single channel
conversion completes. Reading ADRH latches the contents of ADRL
until ADRL is read. Until ADRL is read, all subsequent ADC results will
be lost.
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dress:
$0041
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write: R
R
R
R
R
R
R
R
Reset:
Unaffected by Reset
R = Reserved
Figure 18-4. ADC Data Register High (ADRH)
Left Justified Mode
In right justified mode, this 8-bit result register holds the two MSBs of the
10-bit result. All other bits read as 0. This register is updated each time
a single channel ADC conversion completes. Reading ADRH latches the
contents of ADRL until ADRL is read. Until ADRL is read, all subsequent
ADC results will be lost.
Ad-
dress:
$0041
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
AD9 AD8
Write: R
R
R
R
R
R
R
R
Reset:
Unaffected by Reset
R = Reserved
Figure 18-5. ADC Data Register High (ADRH)
Right Justified Mode
Technical Data
322
Analog-to-Digital Converter (ADC)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor