MC68HC908MR8 Datasheet, PDF (336/372 Pages) Motorola, Inc – Microcontrollers

Break (BRK)
20.6.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from wait mode. The flag is useful in applications
requiring a return to wait mode after exiting from a break interrupt.
Ad-
dress:
$FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
1
0
0
BW
0
Write: R
R
R
R
R
R
Note
R
Reset: 0
0
0
1
0
0
0
0
Note: Writing a logic 0
clears BW.
R
= Reserved
Figure 20-6. SIM Break Status Register (SBSR)
BW — Break Wait Bit
This read/write bit is set when a break interrupt causes an exit from
wait mode. Clear BW by writing a logic 0 to it. Reset clears BW.
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
BW can be read within the break interrupt routine. The user can modify
the return address on the stack by subtracting 1 from it. The example
code shown in Figure 20-7 works if the H register was stacked in the
break interrupt routine. Execute this code at the end of the break
interrupt routine.
Technical Data
336
Break (BRK)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor