MC68HC908MR8 Datasheet, PDF (95/372 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
Reset and System Initialization
Reset Type
POR/LVI
All Others
Table 7-2. PIN Bit Set Timing
Number of Cycles Required to set PIN
4163 (4096 + 64 + 3)
67 (64 + 3)
CGMOUT
RST
IAB
PC
VECT H VECT L
Figure 7-4. External Reset Timing
7.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
(IRST) continues to be asserted for an additional 32 cycles (see
Figure 7-5). An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR (see Figure 7-6).
NOTE:
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST as shown in
Figure 7-5.
IRST
RST
CGMXCLK
IAB
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
VECTOR HIGH
Figure 7-5. Internal Reset Timing
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
95