MC68HC908MR8 Datasheet, PDF (307/372 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
Functional Description
Addr.
Register Name
Bit 7 6
5
4
3
2
1 Bit 0
Read LVI-
LVI Status and Control Regis-
: OUT
0
0
TRPS-
0
0
0
0
$FE0F
ter Write
(LVISCR) :
R
EL
R
R
R
R
R
R
See page 308. _Re-
set:
0
0
0
0
0
0
0
0
R = Reserved
Figure 17-2. LVI I/O Register Summary
17.4.1 Polled LVI Operation
In applications that can operate at V_DD levels below V_LVRX, software can
monitor V_DD by polling the LVIOUT bit. In the configuration register, the
LVIPWR bit must be at logic 1 to enable the LVI module, and the LVIRST
bit must be at logic 0 to disable LVI resets. TRPSEL in the LVISCR
selects V_LVRX. See 5.4 CONFIG Bits.
17.4.2 Forced Reset Operation
In applications that require V_DD to remain above V_LVRX, enabling LVI
resets allows the LVI module to reset the MCU when V_DD falls to the
V_LVRX level and remains at or below that level for nine or more
consecutive CPU cycles. In the CONFIG register, the LVIPWR and
LVIRST bits must be at logic 1 to enable the LVI module and to enable
LVI resets. TRPSEL in the LVISCR selects V_LVRX.
17.4.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU, V_DD must
remain at or below V_LVRX for nine or more consecutive CPU cycles. V_DD
must be above V_LVRX + V_LVHX for only one CPU cycle to bring the MCU
out of reset. TRPSEL in the LVISCR selects V_LVRX + V_LVHX.
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Low-Voltage Inhibit (LVI)
Technical Data
307