MC68HC908MR8 Datasheet, PDF (138/372 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
certain number of clock cycles, n_TRK, is required to ascertain that the
PLL is within the lock mode entry tolerance, ∆_Lock. Therefore, the
acquisition time, t_ACQ, is an integer multiple of n_ACQ/f_RDV, and the
acquisition to lock time, t_AL, is an integer multiple of n_TRK/f_RDV. Also,
since the average frequency over the entire measurement period must
be within the specified tolerance, the total time usually is longer than
t_Lock as calculated above.
In manual mode, it is usually necessary to wait considerably longer than
t_Lock before selecting the PLL clock (see 8.4.3 Base Clock Selector
Circuit) because the factors described in 8.11.2 Parametric Influences
on Reaction Time may slow the lock time considerably.
Technical Data
138
Clock Generator Module (CGM)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor