MC68HC908MR8 Datasheet, PDF (330/372 Pages) Motorola, Inc – Microcontrollers

Break (BRK)
20.3 Features
Features of the break module include:
• Accessible input/output (I/O) registers during the break interrupt
• Central processor unit (CPU) generated break interrupts
• Software-generated break interrupts
• Computer operating properly (COP) disabling during break
interrupts
20.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the microcontroller unit
(MCU) to normal operation. Figure 20-1 shows the structure of the break
module.
20.4.1 Flag Protection During Break Interrupts
The BCFE bit in the system integration module (SIM) break flag control
register (SBFCR) enables software to clear status bits during the break
state.
Technical Data
330
Break (BRK)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor