English
Language : 

MC68HC908MR8 Datasheet, PDF (368/372 Pages) Motorola, Inc – Microcontrollers
status bit — A register bit that indicates the condition of a device.
stop bit — A bit that signals the end of an asynchronous serial transmission.
subroutine — A sequence of instructions to be used more than once in the course of a program.
The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each
place in the main program where the subroutine instructions are needed, a jump or branch to
subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow
of the main program to execute the instructions in the subroutine. When the RTS instruction
is executed, the CPU returns to the main program where it left off.
synchronous — Refers to logic circuits and operations that are synchronized by a common
reference signal.
system integration module (SIM) — One of a number of modules that handle a variety of
control functions in the modular M68HC08 Family. The SIM controls mode of operation,
resets and interrupts, and system clock distribution.
TIM — See timer interface module (TIM).
timer interface module (TIM) — A module used to relate events in a system to a point in time.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a
frequency. Also see acquisition mode.
two’s complement — A means of performing binary subtraction using addition techniques. The
most significant bit of a two’s complement number indicates the sign of the number (1
indicates negative). The two’s complement negative of a number is obtained by inverting
each bit in the number and then adding 1 to the result.
unbuffered — Utilizes only one register for data; new data overwrites current data.
unimplemented memory location — A memory location that is not used. Writing to an
unimplemented location has no effect. Reading an unimplemented location returns an
unpredictable value. Executing an opcode at an unimplemented location causes an illegal
address reset.
V — The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when
a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and
BLT use the overflow bit.
Technical Data
368
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor