MC68HC908MR8 Datasheet, PDF (294/372 Pages) Motorola, Inc – Microcontrollers

Computer Operating Properly (COP)
15.4.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
15.4.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the SIM counter.
15.4.6 COP Disable
The COP disable (COPD) signal reflects the state of the COP disable bit
(COPD) in the configuration register (CONFIG). See 5.4 CONFIG Bits.
15.5 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and
overlaps the reset vector. Writing any value to $FFFF clears the COP
counter and starts a new timeout period. Reading location $FFFF
returns the low byte of the reset vector.
Ad-
dress:
$FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 15-3. COP Control Register (COPCTL)
15.6 Interrupts
The COP does not generate CPU interrupt requests.
Technical Data
294
Computer Operating Properly (COP)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor