MC68HC908MR8 Datasheet, PDF (93/372 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
SIM Bus Clock Control and Generation
7.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 7-3. This clock can come
from either an external oscillator or from the on-chip phase-locked loop
(PLL). See Section 8. Clock Generator Module (CGM).
OSC1
CGMVCLK
PLL
CLOCK
SELECT
÷2
CIRCUIT
BCS
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
MONITOR MODE
USER MODE
CGM
Figure 7-3. CGM Clock Signals
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
7.3.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See Section 8. Clock Generator Module (CGM).
7.3.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 CGMXCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
93