MC68HC908MR8 Datasheet, PDF (115/372 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
Functional Description
Addr.
$005C
Register Name
Bit 7 6
5
4
3
2
1 Bit 0
Read
:
PLLF
1
1
1
1
PLL Control Register
(PCTL)
See page 126.
Write
:
PLLIE
PLLON BCS
R
R
R
R
R
Re-
set:
0
0
1
0
1
1
1
1
Read
:
LOCK
0
0
0
0
$005D
PLL Bandwidth Control Reg-
ister (PBWC)
See page 129.
Write
:
AUTO
R
ACQ XLD
R
R
R
R
Re-
set:
0
0
0
0
0
0
0
0
$005E
Read
:
PLL Programming Register
(PPG)
See page 131.
Write
:
MUL7
Re-
set:
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6
1
VRS5
1
VRS4
0
R = Reserved
Figure 8-2. CGM I/O Register Summary
8.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
8.4.2.1 PLL Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
115