MC68HC908MR8 Datasheet, PDF (97/372 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
Reset and System Initialization
OSC1
PORRST
CGMXCLK
CGMOUT
RST
IAB
4096
CYCLES
32
CYCLES
32
CYCLES
$FFFE
$FFFF
Figure 7-7. POR Recovery
7.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12–4 of the
SIM counter. The SIM counter output, which occurs at least every
2¹³â€“2⁴ CGMXCLK cycles, drives the COP counter. The COP should be
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at
V_DD + V_HI while the MCU is in monitor mode. The COP module can be
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from
becoming disabled as a result of external noise. During a break state,
V_DD + V_HI on the RST pin disables the COP module.
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
97